NoC Verification Engineer - Qualcomm - Guyancourt, France

Company:

Qualcomm France S.A.R.L.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm France-QITC mission is to develop and deploy highly configurable custom-built interconnect hardware IPs (NoCs), software tools, and exploration and verification methodologies so that SoC integration teams can quickly assemble and verify SoCs with the desired Power Performance Area (PPA) characteristics. To this end, QITC technology embraces the complete SoC infrastructure to provide increased SoC performance at minimal cost for integration. Our work is at the backbone of the SoC, interconnecting all major IP solutions.

Qualcomm Interconnect Technology Center (QITC) has been breaking ground in interconnect design for 15 years and continues to innovate and deliver technology in line with the very latest evolutions in SoC design.

QITC NoC solution tools includes a full suite of automated interconnect design and verification tools that improve user productivity. In particular, NoC verification tools include state of the art Verification IPs, UVM benches and scoreboards, used to check NoC assembly and NoC-level features. The UVM bench is automatically generated by the software, allowing to map to all NoC varying topologies and features.

The Job, as part of the NoC Verification tool team, is to provide verification components, benches, and their associated automatization tools, with high quality, high maintainability and compliant with current ASIC verification standards like UVM.

This is a position at a crossroad between software and EDA tool design, verification component design and hardware IP verification.

A short cover letter showing how your profile fits with the position would be appreciated.

Responsibilities:

Responsibilities are to:

Verify NoC-level features.

Develop and maintain the associated benches (UVM) and the software which generates them (python).

Develop and maintain UVM VIPs for NoC communication protocols

Extend and maintain fully automated verification regressions.

The working environment will consist in: Verilog, SystemVerilog, UVM, Python, Linux, Shell, Git, Synopsys verification tools and IA development tools.

Minimum Qualifications * Master’s degree in Science, Engineering, or related field.

Preferred Qualifications

2 years + in hardware design/verification

Experience in using or designing UVM components, bench or VIPs

Additional Skills:

Knowledge of communication protocols such as ARM AMBA protocols would be a plus

Good debugging skills.

Basic knowledge of object-oriented programming.

Eager to learn new technologies and innovative flows.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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