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IMC

ASIC Implementation Specialist

IMC · Development (Group)

Amsterdam

Senior

Embedded & hardware

Last seen 1h ago

Posted
1w ago

Posted on 19 October 2026

Workplace
Not specified

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Salary
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First seen 19 Oct 2026. Last checked 26 Oct, 16:17 UTC. We read each employer's own career page on a cycle and record what changes; this is what we observed, not a verdict on the role.

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As an ASIC Implementation Specialist in our Global Hardware R&D team, you’ll help expand IMC’s ASIC capabilities, building on our existing technology to accelerate time-to-market.

You’ll work on greenfield projects spanning cutting-edge research and production-scale implementations, with multiple overlapping projects each year. This is an opportunity to help shape the future of ASICs at IMC and contribute to technology that will support our trading systems over the next decade.

Your Core Responsibilities:

Take ownership of blocks throughout the RTL-to-GDSII back-end flow: synthesis, floorplanning, clock-tree synthesis, timing optimization and signoff.

Design floorplans and power grids, making key decisions around macro and pin placement, area budgeting and clock-tree optimization.

Drive STA and timing closure for high-performance designs, developing and validating the SDC constraints needed to achieve design goals.

Ensure designs are ready for signoff through power integrity analysis, physical verification, logic equivalence checking and ECOs.

Shape and improve implementation flows around design needs, building automation and scripts that support efficient execution.

Work closely with RTL design, DFT, packaging and foundry teams, using physical implementation insights to influence and improve RTL.

Share your expertise through design reviews and clear documentation.

Your Skills and Experience:

Required Experience:

BS/MS in Electrical or Computer Engineering, with 7+ years of ASIC implementation experience and multiple successful tapeouts.

Strong experience across physical implementation and signoff, including floorplanning, clock-tree synthesis, STA, timing closure and physical verification.

Hands-on experience with Cadence and Siemens implementation and signoff tools.

Strong understanding of CMOS, RC-parasitic extraction and key physical design formats and constraints.

Experience with low-power design flow.

DFT awareness.

Advanced FinFET nodes experience (16/12/7/5).

Preferred Experience:

Experience with custom macro integration.

Knowledge of package/PCB co-design, chiplet or 2.5D/3D integration.

Exposure to machine-learning-driven implementation flows.

RTL coding ability and functional verification experience.

Synthesis and DFT experience.

About Us

IMC is a research-driven trading firm where quantitative modeling, machine learning, and engineering shape how modern markets are traded. A stabilizing force in markets since 1989, we provide liquidity across trading venues, delivering the best outcome in value and risk management to investors. Using our own technology and capital, we build proprietary systems and algorithms that operate across global markets. Our researchers, traders, and engineers work as a collective, combining rapid experimentation, advanced infrastructure, and real-time feedback to turn insight into execution and execution into advantage.

About IMC

IMC's European engineering is split between Amsterdam and a smaller Zug and London presence. Like the other market makers tracked here, expect low-latency systems work rather than conventional web engineering.

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