This role has closed 1w ago. It is no longer on Graphcore's board, so there is nothing left to apply to. The posting is kept here because you saved it or opened it; it is a record, not an offer.

Verified by our engine · Posted 4mo ago

Graphcore

Hardware Validation and Debug Engineer - DDR

Graphcore · Hardware Test Engineering

Bristol

Mid-level

SoftwareBash / ShellPython

Last seen 1w ago

Posted
4mo ago

Posted on 20 May 2026

Workplace
Not specified

Work model not stated

Salary
Not disclosed

Salary range not shared by the company

Visa sponsorship
Not specified

Visa sponsorship details unknown

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Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are expending our labs in Bristol which will play a central role in Graphcore's work building the future of AI computing.

We are looking for a Validation and Debug engineer to work with Architecture, Silicon Engineering, Hardware Engineering and the Firmware team to help create and execute the bring-up and debug of our cutting-edge system platforms. As such you will need to develop a detailed understanding of our silicon and platform products. Your role will be to create and execute Validation and Debug plans of our silicon devices and platforms in systems to show that they will operate correctly over all conditions in the final product. This Validation will also involve debugging of hardware and firmware. You will concentrate on mainly manual testing of systems in the lab with the aid of some automation.

Responsibilities and Duties

Perform Validation and Debug for new hardware platforms.

Debug PCB, power, signal integrity, and interface issues.

Validate and debug high-speed memory interfaces and slow speed interfaces

LPDDR5-9600 memory interfaces

SPI/I2C/I3C/UART

Support LPDDR5-9600 initialization, training, timing optimization, margin analysis, and stability validation.

Analyse DDR timing margins, signal integrity, eye diagrams, and training behaviour.

Identify root causes and drive corrective actions across hardware and firmware domains.

Create bring-up documentation, test procedures, and debug reports.

Working closely with:

PCB design engineers

Power engineers

Signal integrity engineers

Embedded software teams

Essential skills

Hardware Debug

LPDDR validation and tuning

Signal integrity analysis

DDR training and margin analysis

Protocol-level debugging

Root-cause analysis

Low-level system integration

An ability to work independently without daily oversight.

Independently performs board bring-up and subsystem debug

Drives issue resolution across teams.

Use advanced lab instrumentation including:

High-bandwidth oscilloscopes

BERT systems

VNA/TDR equipment

Hands-on experience with:

LPDDR5 memory subsystems

LPDDR5 compliance testing

Desirable skills:

Knowledge of PCBA and system level technologies

Ethernet validation

PCIe

Background knowledge of ATE systems and capabilities. You may not be directly involved with such testing.

The ability to code or script automation and data analysis using appropriate coding languages such as Python, LabView and BASH.

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

About Graphcore

Graphcore designs AI accelerators from Bristol and Cambridge, with a silicon team in Gdańsk. Hardware-heavy: verification, physical design and bring-up.