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ASML

Internship project proposal: Internship

ASML · Interns and Trainees

the Netherlands

Intern

Last seen 5h ago

Posted
3d ago

Posted on 2 October 2026

Workplace
Not specified

Work model not stated

Salary
Not disclosed

Salary range not shared by the company

Visa sponsorship
Not specified

Visa sponsorship details unknown

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Objective

The goal of this internship is to investigate and develop quantum-computing-based approaches for mesh partitioning and graph optimization in plasma simulations. The work will focus on leveraging quantum annealing and hybrid quantum-classical algorithms to improve the efficiency of meshing and domain decomposition techniques used in large-scale plasma modeling.

The internship will contribute to an ongoing ASML/TNO collaboration exploring how emerging quantum computing technologies can accelerate computational workflows relevant to plasma physics and semiconductor manufacturing applications.

Background

Plasma simulations play an important role in understanding physical processes relevant to advanced semiconductor manufacturing, including plasma-material interactions, charged particle transport, and contamination control. Modern plasma models often rely on large computational meshes whose generation, partitioning, and optimization can become computationally expensive as simulation complexity increases.

Recent advances in quantum computing, and particularly quantum annealing, offer novel approaches for solving graph-based optimization problems. Many meshing and domain decomposition challenges can be formulated as graph partitioning problems and translated into Quadratic Unconstrained Binary Optimization (QUBO) models suitable for execution on quantum annealers. However, practical application requires efficient embedding of graph problems onto real quantum hardware and careful integration with classical computational methods.

This internship will investigate how quantum-assisted optimization can be applied to mesh partitioning for plasma simulations and evaluate potential benefits and limitations of current quantum annealing technologies.

Scope & Deliverables

· Study meshing and graph partitioning methods commonly used in plasma simulations.

· Investigate quantum annealing and QUBO-based formulations for mesh partitioning problems.

· Develop and implement graph-based meshing or domain decomposition workflows suitable for hybrid quantum-classical optimization.

· Evaluate embedding strategies for mapping graph partitioning problems onto quantum annealing hardware.

· Benchmark quantum-assisted approaches against classical meshing and partitioning techniques.

· Collaborate with researchers from ASML and TNO on algorithm development and validation.

· Document findings, present results to project stakeholders, and provide recommendations for future research directions.

Period & Duration

Start date: As soon as possible

End date: 31 December 2026

Duration: Approximately 3 to 4 months (depending on start date)

Location: TNO Delft & ASML Veldhoven

This position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology.

Inclusion and diversity

ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company.

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About ASML

ASML is Europe's largest tech company by valuation and the sole maker of the extreme-ultraviolet lithography systems that print the smallest transistors in the world — without it, nothing below a certain chip size gets made anywhere. Almost all its European roles sit in the Netherlands, split between the software that runs the machines and the manufacturing that builds them.

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